In general below sequence is followed in Low Power related design.
1. Save the register/flop o/p.
2. Enable isolation.
3. Clock gating.
4. Shutdown power domain.
5. Wait for specific time period.
6. Switch On power domain.
7. Restore the saved value on register/flop.
8. Clock un-gate.
9. Disable isolation.
1. Save the register/flop o/p.
2. Enable isolation.
3. Clock gating.
4. Shutdown power domain.
5. Wait for specific time period.
6. Switch On power domain.
7. Restore the saved value on register/flop.
8. Clock un-gate.
9. Disable isolation.
really helpful..Thanks
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