How clock gating is used to reduce Dynamic Power consumption?

Clock gating is the effective way to reduce Dynamic/Switching power consumption. When the user knows my domain is in standby state , user can easily gate(block) the clock used in Flip-flops (sequential elements) in that power domain . So when there is no activity on clock , Sequential elements will not have to change their states . Which in turn will reduce the Power consumption as more the switching more power consumption.

Generally clock gating is done by adding extra clock gating logic in the path of original clock . i.e original clock is "clk" and control pin to gate this clock this "clk_cntrl" . So an AND gate logic is inserted which has to i/p "clk" and "clk_cntrl" . And o/p is "clk_gated" , which will will be then used in all sequential logic as final clock.


Verilog code:

assign clk_gate = clk & clk_cntrl ;

always @ (posedge clk_gate) begin
  if (!rst) q <= 0;
 else q <= d;
end


>> This way when domain is going in standby mode, value of "clk_cntrl" can be changed to logic 0. So that signal "clk_gate" will also  become 0 and hence there will not be any switching activity on flop .


>> User can verify that clock gating is done properly or not using writing some custom assertion.

i.e Consider a example where "standby_ctrl" is control pin used to put domain in standby(COA) mode . when "standby_ctrl" is 1 , domain is in standby mode.


So below piece of code can be written in testbench to verify clock gating logic.

always @(standby_ctrl) begin
  if (psw_ctrl)  begin
     assert (clk_gate == 0 );
    else $error ($time,"CLK_GATING not active when domain is in standby(COA) state");
 end
 else begin
   assert (clk_gate == clk );
    else $error ($time,"CLK_GATING  active when domain is in ON state");
 end
end