UPF is language invented to allow user to do Low Power checks parallel to design flow. With UPF user can do Low Power checks at all stages of VLSI flow. i.e From RTL ,Netlist, PG-Netlist. UPF is written at RTL stage . User needs to define the power intent of his/her Design in the UPF file. Then user will take his RTL design and UPF to Synthesis tools like DC . Synthesis tool will add Low Power cells to Netlist Design based on what user has written in his/her UPF.
