Why Isolation is required b/w ON to OFF(Standby) block ?

Generally we see that Isolation is required b/ OFF to ON block. But in some design isolation cells are inserted b/w ON to OFF(More correct to say standby) block as well. This is called as Parking .

This is required for some signals which are having many load in OFF(Standby) block. i.e clock/reset. This will insure that clock/reset does not toggle when domain is in OFF(Standby) state. And which in turn will prevent switching/toggling of many sequential elements in shutdown domain . And hence we can reduce power consumption.

Low Power Sequence

In general below sequence is followed in Low Power related design.

1. Save the register/flop o/p.
2. Enable isolation.
3. Clock gating.
4. Shutdown power domain.
5. Wait for specific time period.
6. Switch On power domain.
7. Restore the saved value on register/flop.
8. Clock un-gate.
9. Disable isolation.

How clock gating is used to reduce Dynamic Power consumption?

Clock gating is the effective way to reduce Dynamic/Switching power consumption. When the user knows my domain is in standby state , user can easily gate(block) the clock used in Flip-flops (sequential elements) in that power domain . So when there is no activity on clock , Sequential elements will not have to change their states . Which in turn will reduce the Power consumption as more the switching more power consumption.

Generally clock gating is done by adding extra clock gating logic in the path of original clock . i.e original clock is "clk" and control pin to gate this clock this "clk_cntrl" . So an AND gate logic is inserted which has to i/p "clk" and "clk_cntrl" . And o/p is "clk_gated" , which will will be then used in all sequential logic as final clock.


Verilog code:

assign clk_gate = clk & clk_cntrl ;

always @ (posedge clk_gate) begin
  if (!rst) q <= 0;
 else q <= d;
end


>> This way when domain is going in standby mode, value of "clk_cntrl" can be changed to logic 0. So that signal "clk_gate" will also  become 0 and hence there will not be any switching activity on flop .


>> User can verify that clock gating is done properly or not using writing some custom assertion.

i.e Consider a example where "standby_ctrl" is control pin used to put domain in standby(COA) mode . when "standby_ctrl" is 1 , domain is in standby mode.


So below piece of code can be written in testbench to verify clock gating logic.

always @(standby_ctrl) begin
  if (psw_ctrl)  begin
     assert (clk_gate == 0 );
    else $error ($time,"CLK_GATING not active when domain is in standby(COA) state");
 end
 else begin
   assert (clk_gate == clk );
    else $error ($time,"CLK_GATING  active when domain is in ON state");
 end
end

Power Switch cells and strategy in Power aware design and UPF

Overview:

• Power Switch cells are used for Power distribution in Power aware design. 
• These are typically inserted by Placement and routing tool (i.e ICC).
• To let tool insert a PSW cells in the design , At RTL stage user needs to define Power switch strategy in UPF using create_power_switch command.

Types of Power switch cells:

Depending on liberty attribute:

1. Fine grain :

• Liberty attribute : switch_cell_type : fine_grain;

2. Coarse grain :

• Liberty attribute : switch_cell_type : coarse_grain;

Depending on Power/Ground Routing:

1. Header switch :

• This is for routing Power Net. PMOS is used for constructing this type of PSW cells as PMOS is good to pass logic 1 .

2. Footer switch :

• This is for routing Ground Net. NMOS is used for constructing this type of PSW cells as NMOS is good to pass logic 1 .

Example: 

UPF:

create_power_switch sw_1 -domain TOP

-output_supply_port {psw_out VDD_PSW}

-input_supply_port {psw_in VDD}

-control_port {ctrl_psw sw_en}

-on_state {PSW_on vin { ctrl_psw }}

-off_state {PSW_off { ! ctrl_psw}}