Wednesday 29 June 2016

What is Isolation cells in Power aware Design?


Why Isolation cell is required in Power Aware Design?
  • Two power domains interact if one contains logic that is the driver of a net and the other contains logic that is a receiver of the same net. When both power domains are powered up, the receiving logic should always see the driving logic’s output as an unambiguous 1 or 0 value, except for a very short time when the value is in transition. The structure of CMOS logic typically ensures that minimal current flow will occur when the input value to a gate is a 1 or 0. However, if the driving logic is powered down, the input to the receiving logic may float between 1 or 0. This can cause significant current to flow through the receiving logic, which can damage the circuit. An undriven input can also cause functional problems if it floats to an unintended logic value.
  • To avoid this problem, isolation cells are inserted at the boundary of a power domain to ensure that receiving logic always sees an unambiguous 1 or 0 value. Isolation may be inserted for an input or for an output of the power domain. An isolation cell operates in two modes: normal mode, in which it acts like a buffer, and isolation mode, in which it clamps its output to a defined value. An isolation enable signal determines the operational mode of an isolation cell at any given time.

Types Of Isolation Cells :

Depending upon the need of user , There are mainly three types of isolation cells.

1. Isolation cell with clamp_value 1:
  • This type of Isolation cells will have function such that it will have o/p of logic 1 , when it is in isolation mode. And when it is in non-isolation mode it will act as buffer i.e simply pass the data to o/p. This is similar to OR gate.
2. Isolation cell with clamp_value 0:
  • This type of Isolation cells will have function such that it will have o/p of logic 0 , when it is in isolation mode. And when it is in non-isolation mode it will act as buffer i.e simply pass the data to o/p.This is similar to AND gate.
3. Latch type Isolation cell:
  • This type of Isolation cells will have function such that it will latch the o/p of isolated port when it is in isolation mode. And when it is in non-isolation mode it will act as buffer i.e simply pass the data to o/p.This is similar to Latch.

13 comments:

  1. Good description, but it can be more easy if any images should be used to understand power domain, how isolation and retention are placed in domain boundary and how they works.

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  2. when will be use clamp0, clamp1, latch type of isolation cells? , can you please give examples

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    1. It depends on the design. i.e signal on which you put isolation cell is connected to other blocks i/p signal . Then you need to check if that input signal is interpreted with which logic value in that block. For example active low reset signal can be isolated with clamp value 1 so that it can not be interpreted wrongly when it is in isolation mode.

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    2. It is based on receiver Logic cell functionality. Mostly In design they will provide default value for Isolation. Retention will hold current data.

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  3. great,recently started working on this domain,i got fundamental idea to understand

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    1. In my code i am seeing like below
      set_isolation_control isolation_signal isolation_sense
      how can we say that iso cell is in isolation mode or normal mode?
      isolation_signal(high)==isolation _sense(default high)-->what mode?
      isolation_signal(low)==isolation _sense(default high)-->what mode?
      isolation_signal(high)==isolation _sense low -->what mode?
      isolation_signal(low)==isolation _sense low -->what mode?

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    2. isolation_signal(high)==isolation _sense(default high)
      -> isolation mode

      isolation_signal(low)==isolation _sense(default high)
      -> Normal mode

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  4. Hi Good one. I have a doubt. When Isolation values are passing to receiver power domain, Do we need to consider as Async signal and do we need to use DoubleFF? Like CDC, RDC any Power Domain Crossing is there?

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    1. Hi Suresh,

      From "isolation value" do you mean isolated signal's value or isolation signal mentioned in the UPF strategy?

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  5. what is this mode?
    isolation_signal(low)==isolation _sense low -->what mode?

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    1. It is isolation mode since sense is low and signal is also low .

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  6. Hi Ravin,
    I have one question :
    What if I dont put isolation cells from On-off module to ON module :
    IF i dont care about signal / Power ; such as passing dont care signal and power i dont have any concern.
    So in this case should i use isolation cells or not.

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    Replies
    1. Isolation is required to prevent leakage current . Which I believe can not be ignored in general .

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