With which supply nwell and pwell (bias) will get connected

If bias analysis is OFF in your UPF.

  pwell of cell will be connected to same supply as primary ground supply.

  nwell of cell will be connected to same supply as primary power supply.

If bias analysis is ON in your UPF.

  pwell of cell will be connected to pwell supply mentioned in the primary supply set of domain.

  nwell of cell will be connected to nwell supply mentioned in the primary supply set of domain.

Example :

======

Design :

====

module top(a,b,c,power,ground,nwell,pwell);

MUX  m1 (a,b,c,power,ground,nwell,pwell);

endmodule

UPF:

===

create_power_domain TOP

create_power_domain PD1 -elements {m1 }

create_supply_set SS1 -function {power VDD_1} -function {ground VSS_1}

create_supply_set SS1 -function {pwell VSS_1p} -update

create_supply_set SS1 -function {nwell VDD_1n} -update

create_power_domain PD1 -supply {primary SS1} -update

Result:

===

If bias analysis is OFF in your UPF.

  pwell will be connected to VSS_1

  nwell will be connected to VDD_1

If bias analysis is ON in your UPF.

  pwell will be connected to VSS_1p

  nwell will be connected to VDD_1n

Default value of ack port of Power Switch (PSW)

By default value on ack port of PSW is logic 1 if PSW o/p state is FULL_ON. And logic 0 if OFF.

What is CORRUPT_ON_ACTIVITY simstate ?

CORRUPT_ON_ACTIVITY name itself indicates that corrupt signal if there is any activity .
It means that any combinational or sequential element can hold the current value until there is any activity on the dependent signals.

let us consider below example to understand the above statement.

Example (combo logic ) :

Design:

module top (input in1,in2,output out);

assign out = in1 & in2;

endmodule

UPF:

create_power_domain TOP

add_power_state TOP.primary -state NORMAL_STATE  { -supply_expr {power==`{FULL_ON, 1.2}}  -simstate NORMAL}

add_power_state TOP.primary -state COA_STATE  { -supply_expr {power==`{FULL_ON, 1.0}}  -simstate CORRUPT_ON_ACTIVITY}

>> So here I have two states of power domain. One is NORMAL and another is CORRUPT_ON_ACTIVITY.

>> So when voltage value of power net of power domain TOP changes to 1.0 volt from 1.2 volt. After that it can hold on the last stable value of signal "out" until there is any change in signal "in1" or "in2".

>> If there is any change in signal "in1" or "in2" when the domain simstate is "CORRUPT_ON_ACTIVITY" , signal "out" will changes to 1'bx.

time = 20 ns   in1 = 1 ; in1 = 1 ; out = 1'b1  ; simstate : NORMAL

time = 22 ns   in1 = 1 ; in1 = 1 ; out = 1'b1  ; simstate : CORRUPT_ON_ACTIVITY

time = 30 ns   in1 = 1 ; in1 = 0 ; out = 1'bx  ; simstate : CORRUPT_ON_ACTIVITY

Example (Sequential logic ) :

Design:
module top (input in1,clk,rst,output out);

always @ (posedge clk, posedge rst) begin
 if (!rst) begin
    out <= 1'b0 ;
 end
 else begin
    out <= in1 ;
  end
end

endmodule

UPF:

create_power_domain TOP

add_power_state TOP.primary -state NORMAL_STATE  { -supply_expr {power==`{FULL_ON, 1.2}}  -simstate NORMAL}

add_power_state TOP.primary -state COA_STATE  { -supply_expr {power==`{FULL_ON, 1.0}}  -simstate CORRUPT_ON_ACTIVITY}

>> So here I have two states of power domain. One is NORMAL and another is CORRUPT_ON_ACTIVITY.

>> So when voltage value of power net of power domain TOP changes to 1.0 volt from 1.2 volt. After that it can hold on the last stable value of signal "out" until there is any change in signal "clk" or "rst".

>> If there is any change in signal "clk" or "rst" when the domain simstate is "CORRUPT_ON_ACTIVITY" , signal "out" will changes to 1'bx.

time =  0 ns   clk = 0 ; rst = 1;  in1 = 1 ;out = 1'bx ; simstate : NORMAL

time = 10 ns  clk = 1 ; rst = 1;   in1 = 1 ; out =1 ; simstate : NORMAL

time = 20 ns  clk = 0 ; rst = 1;   in1 = 1 ;out =1 ; simstate : NORMAL

time = 22 ns  clk = 0 ; rst = 1;   in1 = 1 ; out =1 ; simstate : CORRUPT_ON_ACTIVITY

time = 30 ns  clk = 1 ; rst = 1;   in1 = 1 ; out =1'bx ; simstate : CORRUPT_ON_ACTIVITY

What is Latch based isolation ?

Latch based isolation is similar to latch in architecture.

when user specify  "-clamp_value latch " in set_isolation latch type isolation is used for analysis.

We can mimic RTL behavioural model of latch based isolation as below.


Behavioural model for Latch based isolation :


module ISO_LATCH (data,iso_en,q,VDD,VSS) ;
input data,iso_en;
input VDD,VSS ;  //power and ground pin .
output q;

reg q_latch;


assign q = ((VDD && !VSS )  ? (iso_en ? q_latch : data ) : 1'bx) ;

always @ (VDD,VSS, iso_en,data) begin

  if (!(VDD && !VSS ) ) begin
         q_latch <= 1'bx ;
  end
  else if ( iso_en === 1'bx || iso_en === 1'bz) begin
         q_latch <= 1'bx ;
  end
  else if (iso_en === 1'b1 )
        q_latch <= data ;

end


endmodule

Example:


Let us consider below example to understand the simulation behavior of Latch based isolation.


Design:

module top (input in1,in2,iso_en,output out);

assign out = in1 & in2 ;

endmodule


UPF:

create_power_domain PD1
set_isolation iso_1 -domain PD1 -elements {out} -clamp_value latch  -location self -isolation_signal iso_en -isolation_sense high


Here when "iso_en" signal changes to value 1 , value of signal "out" at that time will be latched until "iso_en" is changes to logic 0 , irrespective of domain primary supply .

Why we need behavioral model+DB cell in Power aware simulation ?

•        Behavioural model is must for simulation tool.

o   Behavioural model is necessary for simulation tool to do functional checks . From DB it cannot retrieve functionality of that DB cell.

o   DB cell is required mainly to get PG pin related information as in non-power aware behavioural model you will not have PG pin information.

•       DB information is optional .

o   If corresponding DB cell info is not provided than DB related checks will not be performed on that module and will be treated as simple Verilog module.

•        Below points can be considered as general guideline.

o   If user have non-power aware behavioural model for DB cell , provide both DB info + behavioural model to simulation tool.

o   If user have Power aware behavioural model for DB cell , Only behavioural model is enough ,provided you do not want to do any DB related checks on it.

Do we need Power State Table (PST) for simulation tool ?

Yes it is needed for Low Power coverage analysis . Simulation tool does coverage analysis based on PST written by user.

Default value of power and ground net

By default state and voltage value for power and ground net should be as follow.